The present invention relates generally to reference diodes and transistors and more specifically to improved low noise diodes and transistors.
Reference diodes are used to generate reference voltages for analog/digital converters, voltage regulated power supplies and bias networks for operational amplifiers. The simplest construction for such a diode as part of an integrated circuit is to use the emitter-base junction of an NPN or PNP bipolar transistor or to abut N+ and P+ diffusions. A limitation to the usefulness of such a reference diode is its noise voltage. Since the doping concentrations are greatest at the surface, the junction breakdown occurs at the surface. Therefore, the properties of the silicon/oxide interface affect the stability and noise of the diode breakdown voltage.
In discussing the problems of manufacturing zener diodes, Hatcher Jr. et al. in U.S. Pat. No. 3,717,516 provides a method for controlling the reverse breakdown characteristics by controlling the oxidation of the surface and the impurity diffusion to modify the impurity-density profile at the surface of the wafer. The high impurity region 16 in combination with the low impurity region 17 produces the desired steep impurity gradient required for high breakdown voltages. Although addressing the problem of controlling the reverse breakdown characteristics of the zener diode, Hatcher Jr. et al. does not discuss or consider solution of the low frequency noise of the diode breakdown voltage.
Another solution of the prior art to avoid the problems of the silicon/oxide interface is to use a buried reference diode. With an extra deep N+ or P+ diffusion capped by an opposite P+ or N+ diffusion, the reference diodes can be constructed which have the maximum doping concentration, and consequently high breakdown voltage occuring well below the silicon-oxide interface. Such subsurface or "buried" diodes are quieter. However, this extra deep N+ or P+ diffusion step makes the associated integrated circuits more expensive to fabricate. A typical example is illustrated in U.S. Pat. No. 3,909,119 to Wholley. This patent is directed to a guarded planar P/N junction semiconductor device wherein the field plate is provided and biased to extend the depletion region into the lighter doped material surrounding the buried junction device. Wholley applies his invention to buried diodes and the base-collector junction of a transistor. This increases the reverse breakdown voltage of the high voltage reference diodes but does not address or correct the low frequency noise problems. Extending the depletion region into the base region moves the maximum field region away from the surface which does tend to lower the noise. However, extending the depletion region into the base region also increases the number of surface trap sites that contribute to noise. Thus a Wholley type of device, although increasing the breakdown voltage, adds to the noise problem.
The use of a gate electrode over the emitter-base junction is known in lateral bipolar transistors as exemplified by U.S. Pat. Nos. 4,089,022 and 4,050,965. The gates in these patents are also used as masks in forming regions of the transistor.